Semiconductor wafer processing plant start-up costs often involve billions of dollars and yet the yield rate for advanced chips can be as low as five percent.
Accordingly, extraordinary efforts have been made to reduce the capital equipment costs and the time and manhours required to manufacture computer chips. One significant device used in the processing of semiconductor wafers is the vacuum chuck which secures the wafer on a photolithographic stepper machine and other machines. The aluminum chuck includes a top surface with a series of lands which must be machined extremely flat to create the lowest possible focal-plane deviation on the front surface of the wafer. Indeed, numerous expensive and time consuming techniques are used to characterize stepper chuck performance. See Goodall and Alverez, "Characterization of Stepper Chuck Performance".
The problems associated with current aluminum vacuum chucks are many. First is the cost. Due to the complicated and time consuming machining, annealing, and polishing processes to render the chuck surface which engages the wafer as flat as possible and, in addition, due to the machining required to include the necessary vacuum lines, a single aluminum vacuum chuck can cost two to three thousand dollars. Prior art vacuum chucks are typically manufactured by machining aluminum, steel, or ceramic materials. Many of these current vacuum chuck materials are very difficult to machine. And, these prior art chucks require a large number of operations involving annealing, quenching, remachining, anodizing, and other process steps. Some vacuum chuck manufacturing processes have as many as twenty-three individual manufacturing steps often involving the use of corrosive chemicals. Therefore, the manufacturing complexity and the cost of prior art vacuum chucks is extremely high.
A second problem associated with current vacuum chucks relates to their poor mechanical stiffness. After the chucks are mounted in a fixture and during production use, the inherent lack of mechanical stiffness results in deformation of the chuck surface from its original plane of flatness. The result of this surface deformation is the introduction of dimensional tolerance errors in the integrated circuit manufacturing process.
A third problem with prior art vacuum chucks is contamination of the substrate secured to the vacuum chuck. Typical vacuum chucks possess excessive surface area and static forces and gravity cause particles to become attracted and adhered to the vacuum chuck face. When these particles become trapped between the wafer and the chuck face during vacuum clamping, the wafer can be distorted. These distortions result in dimensional shifts in the integrated circuit patterns causing a high rate of rejection of the resulting chips. Contaminating particles also tend to become lodged on the surface of the wafer causing defects and rejected chips. The Goodall paper referred to above also delineates the problems associated with particles being trapped between the wafer and the vacuum chuck. Those skilled in the art have taken extraordinary steps to reduce particle contamination. For example, U.S. Pat. No. 4,551,192, incorporated herein by this reference, discloses a method of manufacturing an electrostatic pin chuck, the complexity of which renders it cost prohibitive.
A fourth problem associated with current vacuum chucks relates to thermal expansion. Typical prior art vacuum chucks are made of materials that are not thermally matched to the silicon wafers. When the ambient temperature in the manufacturing area changes, the vacuum chuck expands or contracts at a rate different than silicon wafer. This causes dimensional shifts in the wafer and contributes to a loss of integrated circuit yield.
A fifth problem associated with prior art vacuum chucks is that they do not facilitate alignment of the wafer with respect to the chuck. Current alignment techniques include the placement of alignment marks on the top surface of the wafer. An alignment system then confirms the location of the alignment mark by directing a beam through the wafer to strike the alignment marks. The semiconductor wafer processing steps, however, result in many layers of films which cover the alignment marks making it difficult for the alignment system to detect their position. This results in alignment overlay errors in integrated circuit manufacturing which is also a source of chip rejection since poor alignment causes the integrated chip patterns to drift outside the acceptable dimensional and therefore electrical limits. One of the inventors of the vacuum chuck of the subject invention devised a photoablation technique to remove the layers of resist covering the alignment marks to improve alignment and the micro-lithographic process. See Burggraaf, Lithography trends, Semiconductor International, December, 1986(Cahners Publishing Co.). This technique, however, requires specialized equipment and adds to the semiconductor processing time again seriously impacting costs associated with semiconductor wafer processing.